SH7055S Datasheet, PDF (932/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.8 Serial Communication Interface Timing
Table 26.13 shows serial communication interface timing.
Table 26.13 Serial Communication Interface Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit
Figures
Clock cycle
t_scyc
8
—
t_cyc
Figure 26.16
Clock cycle (clock sync)
t_scyc
12
—
t_cyc
Clock pulse width
t
0.4
0.6
t
sckw
scyc
Input clock rise time
t
—
sckr
3.0
t
cyc
Input clock fall time
t
—
sckf
3.0
t
cyc
Transmit data delay time
t_TxD
—
100
ns
Figure 26.17
Transmit data setup time
t_RxS
100
—
ns
Transmit data hold time
t_RxH
100
—
ns
[Operating precautions]
The inputs and outputs are asynchronous in start-stop synchronous mode, but as shown in figure
26.17, the receive data are judged to have been changed at CK clock rise (two-clock intervals).
The transmit signals change with a reference of CK clock rise (two-clock intervals).
SCK0–SCK4
t_sckw
V_IH
V_IH
V_IL
t_sckr
V_IH
V_IL
t_scyc
t_sckf
V_IH
V_IL
Figure 26.16 SCI Input/Output Timing
Rev.2.0, 07/03, page 894 of 960