SH7055S Datasheet, PDF (989/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

A.2 Register States in Reset and Power-Down States
Table A.2 Register States in Reset and Power-Down States
Reset State Power-Down State
Type
Name
Hardware Software
Power-On Standby Standby
CPU
R0 to R15
Initialized Initialized Held
SR
GBR
VBR
MACH, MACL
PR
PC
FPU
FR0 to FR15
Initialized Initialized Held
FPUL
FPSCR
Interrupt
IPRA to IPRL
controller (INTC) _IOR
Initialized Initialized Held
ISR
User break
UBARH, UBARL
controller (UBC) _{UBAMRH, UBAMRL}
Initialized
Initialized Held
UBBR
UBCR
Bus state
BCR1, BCR2
controller (BSC) _WCR
Initialized Initialized Held
Direct memory
access controller
(DMAC)
SAR0 to SAR3
Initialized
DAR0 to DAR3
DMATCR0 to DMATCR3
Initialized Initialized
CHCR0 to CHCR3
DMAOR
Advanced timer BFR6A-D, BFR7A-D Initialized
unit-II (ATU-II) _{CYLR6A-D, CYLR7A-D}
Initialized Initialized
DCNT8A-P
DSTR
Sleep
Held
Held
Held
Held
Held
Held
Held
Rev.2.0, 07/03, page 951 of 960