SH7055S Datasheet, PDF (479/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 13.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 13.7 Timing of Setting WOVF
Rev.2.0, 07/03, page 441 of 960