SH7055S Datasheet, PDF (834/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Even though an interrupt is requested during SCO download, the interrupt processing is not
executed until download ends. Note that interrupt requests are basically retained, so that on
completion of download, the interrupt processing starts. When more than one type of interrupts
are requested, their priorities are judged by the interrupt controller (INTC), and execution
starts from the interrupt processing with higher priority.
 NMI, UBC, and H-UDI interrupt requests
When these interrupt requests occur during SCO download, their interrupt sources are
retained.
 IRQ interrupt request
Falling-edge detection or low-level detection can be specified for an IRQ interrupt.
• Falling-edge detection is selected: When the falling-edge of IRQ is detected during
SCO download, the interrupt source is retained.
• Low-level detection is selected: When the low-level of IRQ is detected during SCO
download, if the IRQ remains low when download ends, the interrupt processing starts.
If the IRQ is high when download ends, the interrupt source will be canceled.
 On-chip peripheral module interrupt request
An interrupt from an on-chip peripheral module is requested by input of the specified level.
Since the interrupt signal continues to be output unless the interrupt flag is cleared, the
interrupt source is retained.
(2) Interrupts during programming/erasing
Though an interrupt processing can be executed at realtime during programming/erasing of the
downloaded on-chip program, the following limitations and notes are applied.
1. When flash memory is being programmed or erased, both the user MAT and user boot MAT
cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-
chip RAM or external memory. Make sure the flash memory being programmed or erased is
not accessed by the interrupt processing routine. If flash memory is read, the read values are
not guaranteed. If the relevant bank in flash memory that is being programmed or erased is
accessed, the error protection state is entered, and programming or erasing is aborted. If a bank
other than the relevant bank is accessed, the error protection state is not entered but the read
values are not guaranteed.
2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to
provided by the interrupt processing, temporarily save the new program data in another area.
After confirming the completion of programming, save the new program data in the area
specified by FMPDR or change the setting in FMPDR to indicated the other area in which the
new program data was temporarily saved.
3. Make sure the interrupt processing routine does not rewrite the contents of the flash-memory
related registers or data in the downloaded on-chip program area. During the interrupt
processing, do not simultaneously perform RAM emulation, download of the on-chip program
by an SCO request, or programming/erasing.
4. At the beginning of the interrupt processing routine, save the CPU register contents. Before
returning from the interrupt processing, write the saved contents in the CPU registers again.
Rev.2.0, 07/03, page 796 of 960