SH7055S Datasheet, PDF (417/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.4 Interrupts
The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match
interrupts, overflow interrupts, underflow interrupts, and interval interrupts.
11.4.1 Status Flag Setting Timing
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the
IMF bit and ICF bit are set to 1 in the timer status register (TSR), and the TCNT value is
simultaneously transferred to the corresponding GR, ICR, and OSBR.
The timing in this case is shown in figure 11.37.
In the example in figure 11.37, a signal is input from an external pin, and input capture is
performed on detection of a rising edge.
CK
Input capture input
Internal input capture
signal
TCNT
t_TICS (input capture input setup time)
N
GR (ICR)
N
Interrupt status flag
IMF (ICF)
Interrupt request signal
IMI (ICI)
Figure 11.37 IMF (ICF) Setting Timing in Input Capture
Rev.2.0, 07/03, page 379 of 960