SH7055S Datasheet, PDF (161/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

UBAMRL:
Bit: 15
14
13
12
11
10
UBM15 UBM14 UBM13 UBM12 UBM11 UBM10
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
9
UBM9
0
R/W
8
UBM8
0
R/W
Bit:
Initial value:
R/W:
7
UBM7
0
R/W
6
UBM6
0
R/W
5
UBM5
0
R/W
4
UBM4
0
R/W
3
UBM3
0
R/W
2
UBM2
0
R/W
1
UBM1
0
R/W
0
UBM0
0
R/W
The user break address mask register (UBAMR) consists of user break address mask register H
(UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH designates whether to mask any of the break address bits
established in UBARH, and UBAMRL designates whether to mask any of the break address bits
established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset
and in module standby mode. They are not initialized in software standby mode.
• UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits
designate whether to mask the corresponding break address 31 to 16 bits (UBA31 to UBA16)
established in UBARH.
• UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits
designate whether to mask the corresponding break address 15 to 0 bits (UBA15 to UBA0)
established in UBARL.
Bit 15–0: UBMn
0
1
Note: n = 31 to 0
Description
Break address UBAn is included in the break conditions (Initial value)
Break address UBAn is not included in the break conditions
Rev.2.0, 07/03, page 123 of 960