SH7055S Datasheet, PDF (29/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.6 Sample Setup Procedures.................................................................................................. 391
11.7 Usage Notes ...................................................................................................................... 406
11.8 ATU-II Registers and Pins ................................................................................................ 419
Section 12 Advanced Pulse Controller (APC)...................................................421
12.1 Overview........................................................................................................................... 421
12.1.1 Features................................................................................................................ 421
12.1.2 Block Diagram ..................................................................................................... 422
12.1.3 Pin Configuration................................................................................................. 423
12.1.4 Register Configuration......................................................................................... 423
12.2 Register Descriptions ........................................................................................................ 424
12.2.1 Pulse Output Port Control Register (POPCR)...................................................... 424
12.3 Operation .......................................................................................................................... 425
12.3.1 Overview.............................................................................................................. 425
12.3.2 Advanced Pulse Controller Output Operation ..................................................... 426
12.4 Usage Notes ...................................................................................................................... 429
Section 13 Watchdog Timer (WDT)..................................................................431
13.1 Overview........................................................................................................................... 431
13.1.1 Features................................................................................................................ 431
13.1.2 Block Diagram ..................................................................................................... 432
13.1.3 Pin Configuration................................................................................................. 432
13.1.4 Register Configuration......................................................................................... 433
13.2 Register Descriptions ........................................................................................................ 433
13.2.1 Timer Counter (TCNT)........................................................................................ 433
13.2.2 Timer Control/Status Register (TCSR) ................................................................ 434
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 436
13.2.4 Register Access.................................................................................................... 437
13.3 Operation .......................................................................................................................... 438
13.3.1 Watchdog Timer Mode ........................................................................................ 438
13.3.2 Interval Timer Mode............................................................................................ 440
13.3.3 Timing of Setting the Overflow Flag (OVF) ....................................................... 440
13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 441
13.4 Usage Notes ...................................................................................................................... 442
13.4.1 TCNT Write and Increment Contention .............................................................. 442
13.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 442
13.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 442
13.4.4 System Reset by WDTOVF Signal...................................................................... 443
13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 443
13.4.6 Manual Reset in Watchdog Timer ....................................................................... 443
Section 14 Compare Match Timer (CMT).........................................................445
14.1 Overview........................................................................................................................... 445
Rev.2.0, 07/03, page xxix of xxxviii