SH7055S Datasheet, PDF (551/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.4 SCI Interrupt Sources and the DMAC
The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI). Table 15.12 lists the interrupt sources and indicates their
priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial
control register (SCR). Each interrupt request is sent separately to the interrupt controller.
TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access
controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes
data in the transmit data register (TDR).
RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data.
RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR).
ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC.
TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the
TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the
transmit operation is complete.
Table 15.12 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
DMAC Activation
No
Yes
Yes
No
Priority
High
Low
Rev.2.0, 07/03, page 513 of 960