SH7055S Datasheet, PDF (889/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

24.2.2 System Control Register (SYSCR)
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
— AUDSRST RAME
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R/W
R/W
The system control register (SYSCR) is an 8-bit readable/writable register that performs AUD
software reset control and enables or disables access to the on-chip RAM.
SYSCR is initialized to H'01 by a power-on reset.
• Bit 7—Reserved: The read value is not defined. The write value should always be 0.
• Bits 6 to 2—Reserved: These bits always read 0. The write value should always be 0.
• Bit1— AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting
AUDSRST bit to 1 places, the AUD module in the power-on reset state.
Bit 1: AUDSRST Description
0
AUD reset state cleared
1
AUD reset state entered
(Initial value)
• Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When
RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM
cannot be accessed. In this case, a read or instruction fetch from on-chip RAM will return an
undefined value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that
attempts to access on-chip RAM immediately after the SYSCR write instruction, as normal
access cannot be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction
immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an on-
chip RAM access instruction is placed immediately after the SYSCR write instruction.
Bit 0: RAME
0
1
Description
On-chip RAM disabled
On-chip RAM enabled
(Initial value)
Rev.2.0, 07/03, page 851 of 960