SH7055S Datasheet, PDF (676/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

19.4.3 Operation
Operation starts in RAM monitor mode AUDMD is driven high after AUDRST has been asserted,
then AUDRST is negated.
Figure 19.5 shows an example of a read operation, and figure 19.6 an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 19.2, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (0000).
When execution is completed, the Ready flag (0001) is returned (figures 19.5 and 19.6). Table
19.2 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 19.7).
If a command other than the above is input in DIR, the AUD treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the
Ready flag to 1 (figure 19.7).
Table 19.2 Ready Flag Format
Bit 3
Fixed at 0
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Bus error
Bit 0
0: Not ready
1: Ready
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
3. Longword access to on-chip I/O 8-bit space
4. Access to external space in single-chip mode
AUDCK
AUDATAn
0000 1000 A3–A0
DIR
Input
Input/output switchover
A31–A28
0000
Not ready
0001
Ready
0001 0001 D3–D0 D7–D4
Ready Ready
Output
Figure 19.5 Example of Read Operation (Byte Read)
Rev.2.0, 07/03, page 638 of 960