SH7055S Datasheet, PDF (399/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

To perform internal interrupts by compare-match or compare-match flag polling processing
without performing compare-match output, designate the corresponding compare-match output
pin as a general I/O pin and select 1 output, 0 output, or toggle output on compare-match in TIOR.
Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match
operations unconditionally. However, there are no corresponding output pins. If the appropriate
TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs.
Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a
compare-match occurs. In this case, settings should be made in the trigger mode register
(TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR).
An example of compare-match operation is shown in figure 11.15.
In the example in figure 11.15, channel 1 is activated, and external output is performed with toggle
output specified for GR1A, 1 output for GR1B, and 0 output for GR1C.
Pø
TCNT1
Clock
TCNT1 003C
003D
003E
003F
0040
007E
GR1A–1C
003E
TIO1A
007F
0080
0081
0082
0083
0084
0085
0081
TIO1B
TIO1C
TSR1
IMF1A–1D
Channel 8
start/terminate
trigger signal
Cleared by software
Cleared by software
Figure 11.15 Compare-Match Operation
11.3.4 Input Capture Function
If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to
GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) in channels 1 to 5
and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to
TIOR5, TIOR11), input capture is performed when an edge is input at the corresponding external
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