SH7055S Datasheet, PDF (341/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 6—A/D0 / A/D1 Converter Interval Activation Bit 12A/12B (ITVA12A/ITVA12B): A/D0
or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to
bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVA12x, and the result is
output to the A/D0 or A/D1 converter as an activation signal.
Bit 6: ITVA12x
0
1
x = A or B
Description
A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is disabled
(Initial value)
A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is enabled
• Bit 5—A/D0 / A/D1 Converter Interval Activation Bit 11A/11B (ITVA11A/ITVA11B): A/D0
or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to
bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVA11x, and the result is
output to the A/D0 or A/D1 converter as an activation signal.
Bit 5: ITVA11x
0
1
x = A or B
Description
A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is disabled
(Initial value)
A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is enabled
• Bit 4—A/D0 / A/D1 Converter Interval Activation Bit 10A/10B (ITVA10A/ITVA10B): A/D0
or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to
bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVA10x, and the result is
output to the A/D0 or A/D1 converter as an activation signal.
Bit 4: ITVA10x
0
1
x = A or B
Description
A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is disabled
(Initial value)
A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is enabled
Rev.2.0, 07/03, page 303 of 960