SH7055S Datasheet, PDF (134/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.1.2 Block Diagram
Figure 7.1 is a block diagram of the INTC.
NMI
Input
control
CPU/
DMAC
request
judg-
ment
Priority
ranking
judg-
ment
Com-
parator
UBC
H-UDI
DMAC
ATU-II
CMT
A/D
SCI
WDT
HCAN
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IPR
ISR
IPRA–IPRL
Module bus
Bus
interface
INTC
UBC: User break controller
H-UDI: High-performance user debug
interface
DMAC: Direct memory access controller
ATU-II: Advanced timer unit
CMT: Compare match timer
A/D: A/D converter
SCI: Serial communication interface
WDT: Watchdog timer
HCAN: Controller area network
ICR: Interrupt control register
ISR: IRQ status register
IPRA–IPRL: Interrupt priority level setting registers A to L
SR: Status register
Figure 7.1 INTC Block Diagram
Rev.2.0, 07/03, page 96 of 960