SH7055S Datasheet, PDF (30/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

14.1.1 Features................................................................................................................ 445
14.1.2 Block Diagram ..................................................................................................... 446
14.1.3 Register Configuration......................................................................................... 447
14.2 Register Descriptions ........................................................................................................ 448
14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 448
14.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 449
14.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 450
14.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 451
14.3 Operation .......................................................................................................................... 451
14.3.1 Cyclic Count Operation ....................................................................................... 451
14.3.2 CMCNT Count Timing........................................................................................ 452
14.4 Interrupts........................................................................................................................... 452
14.4.1 Interrupt Sources and DTC Activation ................................................................ 452
14.4.2 Compare Match Flag Set Timing......................................................................... 452
14.4.3 Compare Match Flag Clear Timing ..................................................................... 453
14.5 Usage Notes ...................................................................................................................... 454
14.5.1 Contention between CMCNT Write and Compare Match................................... 454
14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 455
14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 456
Section 15 Serial Communication Interface (SCI) ............................................457
15.1 Overview........................................................................................................................... 457
15.1.1 Features................................................................................................................ 457
15.1.2 Block Diagram ..................................................................................................... 458
15.1.3 Pin Configuration................................................................................................. 459
15.1.4 Register Configuration......................................................................................... 460
15.2 Register Descriptions ........................................................................................................ 461
15.2.1 Receive Shift Register (RSR)............................................................................... 461
15.2.2 Receive Data Register (RDR) .............................................................................. 462
15.2.3 Transmit Shift Register (TSR) ............................................................................. 462
15.2.4 Transmit Data Register (TDR)............................................................................ 463
15.2.5 Serial Mode Register (SMR)................................................................................ 463
15.2.6 Serial Control Register (SCR).............................................................................. 466
15.2.7 Serial Status Register (SSR)................................................................................. 470
15.2.8 Bit Rate Register (BRR)....................................................................................... 474
15.2.9 Serial Direction Control Register (SDCR)........................................................... 481
15.2.10 Inversion of SCK Pin Signal................................................................................ 482
15.3 Operation .......................................................................................................................... 482
15.3.1 Overview.............................................................................................................. 482
15.3.2 Operation in Asynchronous Mode ....................................................................... 484
15.3.3 Multiprocessor Communication........................................................................... 494
15.3.4 Synchronous Operation........................................................................................ 502
15.4 SCI Interrupt Sources and the DMAC .............................................................................. 513
Rev.2.0, 07/03, page xxx of xxxviii