SH7055S Datasheet, PDF (501/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.2.4 Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in
TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing
the next transmit data in TDR during serial transmission from TSR.
The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and
in hardware standby mode and software standby mode. It is not initialized by a manual reset.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
15.2.5 Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset, and
in hardware standby mode and software standby mode. It is not initialized by a manual reset.
Bit: 7
6
5
4
3
2
1
0
C/A CHR
PE
O/E STOP MP CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode
Synchronous mode
(Initial value)
Rev.2.0, 07/03, page 463 of 960