SH7055S Datasheet, PDF (456/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

ATU Pin Setting: When a port is set to the ATU pin function, the following points must be noted
because input capture or count operation may occur.
When using a port for input capture input, the corresponding TIOR register must be in the input
capture disabled state when the port is set. Regarding channel 10 TI10 input, TCR10 must be in
the TI10 input disabled state when the port is set. When using a port for external clock input, the
STR bit for the corresponding channel must be in the count operation disabled state when the port
is set. When using a port for event input, the corresponding TCR register must be in the count
operation disabled state when the port is set.
Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using
TCLKB and TI10 input, only one pin should be enabled.
Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM
address for which address bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF,
H'00003000 to H'000037FF, H'00005000 to H'000057FF, ..., H'0007F000 to H'0007F7FF, ...,
H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle, the value, or
part of the value, written to ROM will be written to the ATU register. The following measures
should be taken to prevent this.
• Do not perform a CPU write to a ROM address immediately after an ATU register write cycle.
For example, an instruction arrangement in which an MOV instruction that writes to the ATU
is located at an even-word address (4n address), and is immediately followed by an MOV
instruction that writes to a ROM area, will meet the bug conditions.
• Do not perform an AUD write to any of the above ROM addresses immediately after an ATU
register write cycle. For example, in the case of a write to overlap RAM when using the RAM
emulation function, the write should be performed to the on-chip RAM area address, not the
overlapping ROM area address.
• Do not perform a DMAC write to an ATU register when a ROM address write operation
occurs.
Rev.2.0, 07/03, page 418 of 960