SH7055S Datasheet, PDF (371/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the
trigger. In this case, the corresponding IMF bit in TSR is not set.
When a general register is used for output compare, the GR value and free-running counter
(TCNT) value are constantly compared, and when both values match, the IMF bit in the timer
status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR.
GRIIA and GR11B compare-match signals are transmitted to the advanced pulse controller
(APC). For details, see section 12, Advanced Pulse Controller (APC).
The GR registers can only be accessed by a word read or write.
The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and
software standby mode.
General Registers 9A to 9F (GR9A to GR9F)
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
These GR registers are 8-bit readable/writable registers with a compare-match function.
The GR value and event counter (ECNT) value are constantly compared, and when both values
match a compare-match signal is generated and the next edge is input, the corresponding CMF bit
in TSR is set to 1.
In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D
compare-matches. This function is set by TRG3xEN in the timer control register (TCR).
The GR registers can be accessed by a byte read or write.
The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and
software standby mode.
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