SH7055S Datasheet, PDF (306/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 0—Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A
input capture or compare-match. The flag is not set in PWM mode.
Bit 0: IMF3A
0
1
Description
[Clearing condition]
(Initial value)
When IMF3A is read while set to 1, then 0 is written to IMF3A
[Setting conditions]
• When the TCNT3 value is transferred to GR3A by an input capture signal
while GR3A is functioning as an input capture register. However, IMF3A is
not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3A while GR3A is functioning as an output compare
register
Timer Status Registers 6 and 7 (TSR6, TSR7)
TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count
status, and cycle register compare status.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
UDxD
0
R
6
UDxC
0
R
5
UDxB
0
R
Note: * Only 0 can be written to clear the flag.
x = 6 or 7
4
UDxA
0
R
3
2
1
0
CMFxD CMFxC CMFxB CMFxA
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)*
UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count
operation.
Bit 7: UD6D
0
1
Description
Free-running counter TCNT6D operates as an up-counter
Free-running counter TCNT6D operates as a down-counter
Rev.2.0, 07/03, page 268 of 960