SH7055S Datasheet, PDF (659/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.3 Register Descriptions
18.3.1 Instruction Register (SDIR)
Bit: 15
14
13
12
11
10
9
8
TS3
TS2
TS1
TS0
—
—
—
—
Initial value: 1
1
1
1
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The instruction register (SDIR) is a 16-bit register that can be read, but not written to, by the CPU.
H-UDI instructions can be transferred to SDIR from TDI by serial input. SDIR can be initialized
by the TRST signal, but is not initialized by a reset or in software standby mode.
Instructions transferred to SDIR must be 4 bits in length. If an instruction exceeding 4 bits is input,
the last 4 bits of the serial data will be stored in SDIR.
Rev.2.0, 07/03, page 621 of 960