SH7055S Datasheet, PDF(230/1002 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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SH7055S Datasheet, PDF (230/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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â¢ Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated

input capture register. The output compare registers can also be selected for one-shot pulse

offset in combination with the channel 8 down-counter.

ï£§ General registers (GR2AâH) can be used as input capture or output compare registers

ï£§ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle

output

ï£§ Input capture function: Rising-edge, falling-edge, or both-edge detection

ï£§ Channel 0 input signal (TI0A) can be captured as trigger

ï£§ Provision for forcible cutoff of channel 8 down-counters (DCNT8I to P)

ï£§ Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated

â¢ Channels 3 to 5 each have four general registers, allowing the following operations:

ï£§ Selection of input capture, output compare, PWM mode

ï£§ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle

output

ï£§ Input capture function: Rising-edge, falling-edge, or both-edge detection

ï£§ Channel 9 compare-match signal can be captured as trigger (channel 3 only)

ï£§ Compare-match interrupts/capture interrupts can be generated

â¢ Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers,

allowing the following operations:

ï£§ Any cycle and duty from 0 to 100% can be set

ï£§ Duty buffer register value transferred to duty register every cycle

ï£§ Interrupts can be generated every cycle

ï£§ Complementary PWM output can be set (channel 6 only)

â¢ Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following

operations:

ï£§ One-shot pulse generation by down-counter

ï£§ Down-counter can be rewritten during count

ï£§ Interrupt can be generated at end of down-count

ï£§ Offset one-shot pulse function available

ï£§ Can be linked to channel 1 and 2 output compare functions

ï£§ Reload function can be set to eight 16-bit down counters (DCNT8I to DCNT8P)

â¢ Channel 9 has six event counters and six general registers, allowing the following operations:

ï£§ Event counters can be cleared by compare-match

ï£§ Rising-edge, falling-edge, or both-edge detection available for external input

ï£§ Compare-match signal can be input to channel 3

Rev.2.0, 07/03, page 192 of 960

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