SH7055S Datasheet, PDF (206/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the
DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all
channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a
0 write after a 1 read.
Bit 1: NMIF
0
1
Description
No NMI interrupt, DMA transfer enabled
[Clearing condition]
Write NMIF = 0 after reading NMIF = 1
NMI has occurred, DMC transfer disabled
[Setting condition]
NMI interrupt occurrence
(Initial value)
• Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR register for the corresponding channel are set to 1, that
channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels
are suspended.
Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is
disabled if the NMIF or AE bit in DMAOR is set to 1.
Bit 0: DME
0
1
Description
Operation disabled on all channels
Operation enabled on all channels
(Initial value)
Rev.2.0, 07/03, page 168 of 960