SH7055S Datasheet, PDF (249/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.1.4 Block Diagrams
Overall Block Diagram of ATU-II: Figure 11.1 shows an overall block diagram of the ATU-II.
TCLKA
TCLKB
IC/OC control
I/O interrupt
control
Counter and register control,
and comparator
Interrupts
Inter-module
connection
signals
External pins
Inter-module
address bus
........
P
Module data bus
Inter-module
data bus
Legend:
TSTR1, 2, 3: Timer start registers (8 bits)
Interrupts:
ITV0–ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3–OVI5, OVI11, ICI0A–ICI0D, IMI1A–IMI1H,
CMI1, IMI2A–IMI2H, CMI2A–CMI2H, IMI3A–IMI3D, IMI4A–IMI4D, IMI5A–IMI5D, CMI6A–CMI6D,
CMI7A–CMI7D, OSI8A–OSI8P, CMI9A–CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A,
IMI11B
External pins:
TI0A–TI0D, TIO1A–TIO1H, TIO2A–TIO2H, TIO3A–TIO3D, TIO4A–TIO4D, TIO5A–TIO5D,
TO6A–TO6D, TO7A–TO7D, TO8A–TO8P, TI9A–TI9F, TI10, TIO11A–TIO11B
Inter-module connection signals:
Signals to A/D converter, signals to direct memory access controller (DMAC),
signals to advanced pulse controller (APC)
Figure 11.1 Overall Block Diagram of ATU-II
Rev.2.0, 07/03, page 211 of 960