SH7055S Datasheet, PDF (770/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

21.12.3 Port L Port Register (PLPR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
– – PL13 PL12 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
PR PR PR PR PR PR PR PR PR PR PR PR PR PR
Initial value: 0 0 * * * * * * * * * * * * * *
R/W: R R R R R R R R R R R R R R R R
Note: * The initial value is 1 when the PL13 to PL0 pins are high, and it is 0 when the pins are low.
The port L port register (PLPR) is a 16-bit read-only register that always stores the value of the
port L pins. The CPU cannot write data to this register. Bits PL13PR to PL0PR correspond to pins
PL13/IRQOUT to PL0/TI10. If PLPR is read, the corresponding pin values are returned.
• Bits 15 and 14: Reserved: These bits are always read as 0.
• Bits 13 to 0: Port L13 to L0 Port Register (PL13PR to PL0PR)
PL13PR to PL0PR Description
0
Low-level signals are output from or input to the PL13 to PL0 pins.
1
High-level signals are output from or input to the PL13 to PL0 pins.
21.13 POD (Port Output Disable) Control
The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0)
can be controlled by the POD (port output disable) pin input level. However, this function is
enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated
as general output ports.
Output buffer control by means of POD is performed asynchronously from bus cycles.
POD
0
1
Address Bus Pins (A20 to A0) and
Data Bus Pins (D15 to D0) (when designated as output ports)
Enabled (high-impedance)
Disabled (general output)
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