SH7055S Datasheet, PDF (835/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

5. When a transition is made to sleep mode or software standby mode in the interrupt processing
routine, the error protection state is entered and programming/erasing is aborted.
If a transition is made to the reset state, the reset signal should only be released after providing
a reset input over a period longer than the normal 100 µs to reduce the damage to flash
memory.
22.8.3 Other Notes
1. Download time of on-chip program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock
frequency is 40 MHz, the download for each program takes approximately 75 µs at maximum.
2. User branch processing intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 22.11 lists the maximum and minimum intervals for
initiating the user branch processing when the CPU clock frequency is 40 MHz.
Table 22.11 Initiation Intervals of User Branch Processing
Processing Name
Programming
Erasing
Maximum Interval
Approximately 1 ms
Approximately 5 ms
Minimum Interval
Approximately 19 µs
Approximately 19 µs
Table 22.12 lists the maximum and minimum periods until the user branch processing is initiated
when the CPU clock frequency is 40 MHz.
Table 22.12 Required Period for Initiating User Branch Processing
Processing
Programming
Erasing
Max.
Approximately 113 µs
Approximately 85 µs
Min.
Approximately 113 µs
Approximately 45 µs
3. Write to flash-memory related registers by AUD or DMAC
While an instruction in on-chip RAM is being executed, the AUD or DMAC can write to the
SCO bit in FCCS that is used for a download request or FMATS that is used for MAT
switching. Make sure that these registers are not accidentally written to, otherwise an on-chip
program may be downloaded and damage RAM or a MAT switchover may occur and the CPU
get out of control.
4. State in which AUD operation is disabled and interrupts are ignored
In the following modes or period, the AUD is in module standby mode and cannot operate.
The NMI or maskable interrupt requests are ignored; they are not executed and the interrupt
sources are not retained.
Rev.2.0, 07/03, page 797 of 960