SH7055S Datasheet, PDF (485/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

14.1.3 Register Configuration
Table 14.1 summarizes the CMT register configuration.
Table 14.1 Register Configuration
Channel Name
Abbreviation R/W
Initial
Value Address
Access Size
(Bits)
Shared Compare match timer CMSTR
start register
R/W H'0000 H'FFFFF710 8, 16, 32
0
Compare match timer CMCSR0
R/(W)* H'0000 H'FFFFF712 8, 16, 32
control/status register 0
Compare match timer CMCNT0
counter 0
R/W H'0000 H'FFFFF714 8, 16, 32
Compare match timer CMCOR0
constant register 0
R/W H'FFFF H'FFFFF716 8, 16, 32
1
Compare match timer CMCSR1
R/(W)* H'0000 H'FFFFF718 8, 16, 32
control/status register 1
Compare match timer CMCNT1
counter 1
R/W H'0000 H'FFFFF71A 8, 16, 32
Compare match timer CMCOR1
constant register 1
R/W H'FFFF H'FFFFF71C 8, 16, 32
Notes: With regard to access size, four of five cycles are required for byte access and word
access, and eight or nine cycles for longword access.
* Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags.
Rev.2.0, 07/03, page 447 of 960