SH7055S Datasheet, PDF (185/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Operation cannot be guaranteed if such an access is made.
• Bits 15 to 4—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed
if 1 is written.
• Bit 3—RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory
emulation by RAM (table 9.4).
When 1 is written to this bit, all flash memory blocks are write/erase-protected.
This bit is ignored in modes with on-chip ROM disabled.
• Bits 2 to 0—RAM Area Specification (RAM2 to RAM0): These bits are used together with the
RAMS bit to designate the flash memory area to be overlapped onto RAM (table 9.4).
Table 9.4 RAM Area Setting Method
RAM Area
H'FFFF6000 to H'FFFF6FFF
H'00000000 to H'00000FFF
H'00001000 to H'00001FFF
H'00002000 to H'00002FFF
H'00003000 to H'00003FFF
H'00004000 to H'00004FFF
H'00005000 to H'00005FFF
H'00006000 to H'00006FFF
H'00007000 to H'00007FFF
*: Don’t care
Bit 3: RAMS Bit 2: RAM2 Bit 1: RAM1 Bit 0: RAM0
0
*
*
*
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Rev.2.0, 07/03, page 147 of 960