SH7055S Datasheet, PDF (319/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by
OVF1A in TSR1A when OVF1A is set to 1.
Bit 8: OVE1A
0
1
Description
OVI1A interrupt requested by OVF1A is disabled
OVI1A interrupt requested by OVF1A is enabled
(Initial value)
• Bit 7—Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables
interrupt requests by IMF1H in TSR1A when IMF1H is set to 1.
Bit 7: IME1H
0
1
Description
IMI1H interrupt requested by IMF1H is disabled
IMI1H interrupt requested by IMF1H is enabled
(Initial value)
• Bit 6—Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables
interrupt requests by IMF1G in TSR1A when IMF1G is set to 1.
Bit 6: IME1G
0
1
Description
IMI1G interrupt requested by IMF1G is disabled
IMI1G interrupt requested by IMF1G is enabled
(Initial value)
• Bit 5—Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables
interrupt requests by IMF1F in TSR1A when IMF1F is set to 1.
Bit 5: IME1F
0
1
Description
IMI1F interrupt requested by IMF1F is disabled
IMI1F interrupt requested by IMF1F is enabled
(Initial value)
• Bit 4—Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables
interrupt requests by IMF1E in TSR1A when IMF1E is set to 1.
Bit 4: IME1E
0
1
Description
IMI1E interrupt requested by IMF1E is disabled
IMI1E interrupt requested by IMF1E is enabled
(Initial value)
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