SH7055S Datasheet, PDF (215/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

1st and 2nd bus
cycles
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The SAR3 value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. If data
bus is 16 bits wide when accessed to an external memory space, two bus cycles are necessary.
3rd bus cycle
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The value in the temporary buffer is taken as the address, and data is read from the transfer source
module to the data buffer.
4th bus cycle
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The DAR3 value is taken as the address, and the value in the data buffer is written to the transfer
destination module.
Note: Memory, transfer source, and transfer destination modules are shown here.
In practice, any connection can be made as long as it is within the address space.
Figure 10.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External
Memory Space)
Rev.2.0, 07/03, page 177 of 960