SH7055S Datasheet, PDF (324/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 0—Input Capture/Compare-Match Interrupt Enable 2A (IME2A): Enables or disables
interrupt requests by IMF2A in TSR2A when IMF2A is set to 1.
Bit 0: IME2A
0
1
Description
IMI2A interrupt requested by IMF2A is disabled
IMI2A interrupt requested by IMF2A is enabled
(Initial value)
TIER2B: TIER2B controls enabling/disabling of channel 2 compare-match and overflow
interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVE2B
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit:
Initial value:
R/W:
7
CME2H
0
R/W
6
CME2G
0
R/W
5
CME2F
0
R/W
4
CME2E
0
R/W
3
CME2D
0
R/W
2
CME2C
0
R/W
1
CME2B
0
R/W
0
CME2A
0
R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 2B (OVE2B): Enables or disables interrupt requests by
OVF2B in TSR2B when OVF2B is set to 1.
Bit 8: OVE2B
0
1
Description
OVI2B interrupt requested by OVF2B is disabled
OVI2B interrupt requested by OVF2B is enabled
(Initial value)
• Bit 7—Compare-Match Interrupt Enable 2H (CME2H): Enables or disables interrupt requests
by CMF2F in TSR2B when CMF2H is set to 1.
Bit 7: CME2H
0
1
Description
CMI2H interrupt requested by CMF2H is disabled
CMI2H interrupt requested by CMF2H is enabled
(Initial value)
Rev.2.0, 07/03, page 286 of 960