SH7055S Datasheet, PDF (622/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Three sample-and-hold circuits
A sample-and-hold circuit is built into each A/D converter module (AD/0, AD/1, and AD/2),
simplifying the configuration of external analog input circuitry.
• A/D conversion interrupts and DMA function supported
An A/D conversion interrupt request (ADI) can be sent to the CPU at the end of A/D
conversion (ADI0: A/D0 interrupt request; ADI1: A/D1 interrupt request; ADI2: A/D2
interrupt request). Also, the DMAC can be activated by an ADI interrupt request.
• Two kinds of conversion activation
 Software or external trigger (ADTER0, ATU-II (ITVRR2A)) can be selected (A/D0)
 Software or external trigger (ADTGR0, ATU-II (ITVRR2B)) can be selected (A/D1)
 Software or external trigger (ADTGR1, ATU-II (ITVRR1)) can be selected (A/D2)
• ADEND output
Conversion timing can be monitored with the ADEND output pin when using channel 31 in
scan mode.
17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the A/D converter.
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