SH7055S Datasheet, PDF (155/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
Interrupt acceptance
5 + m1 + m2 + m3
3
3 m1 m2 1 m3 1
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed
according to the results of decoding).
M: Memory access (data in memory is accessed).
Figure 7.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted
Rev.2.0, 07/03, page 117 of 960