SH7055S Datasheet, PDF (491/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 14.4 CMF Set Timing
14.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 14.5
shows the timing when the CMF bit is cleared by the CPU.
CMCSR write cycle
T1
T2
Pφ
CMF
Figure 14.5 Timing of CMF Clear by the CPU
Rev.2.0, 07/03, page 453 of 960