SH7055S Datasheet, PDF (358/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.13 One-Shot Pulse Terminate Register (OTR)
The one-shot pulse terminate register (OTR) is a 16-bit register. The ATU-II has one OTR register
in channel 8.
Bit:
Initial value:
R/W:
15
OTEP
0
R/W
14
OTEO
0
R/W
13
OTEN
0
R/W
12
OTEM
0
R/W
11
OTEL
0
R/W
10
OTEK
0
R/W
9
OTEJ
0
R/W
8
OTEI
0
R/W
Bit:
Initial value:
R/W:
7
OTEH
0
R/W
6
OTEG
0
R/W
5
OTEF
0
R/W
4
OTEE
0
R/W
3
OTED
0
R/W
2
OTEC
0
R/W
1
OTEB
0
R/W
0
OTEA
0
R/W
OTR is a 16-bit readable/writable register that enables or disables forced termination of channel 8
one-shot pulse output by channel 1 and 2 compare-match signals. When one-shot pulse output is
forcibly terminated, the corresponding DSTR bit and down-counter are cleared, and the
corresponding TSR8 bit is set. The channel 1 one-shot pulse terminate signal is generated by
GR1A to GR1H compare-matches and OCR1 compare-match (see TRGMDR). The channel 2
one-shot pulse terminate signal is generated by GR2A to GR2H compare-matches. To generate the
terminate signal with GR1A to GR1H and GR2A to GR2H, select the respective compare-matches
in TIOR1A to TIOR1D.
OTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 15—One-Shot Pulse Terminate Enable P (OTEP): Enables or disables forced termination
of output by channel 2 down-counter terminate trigger H.
Bit 15: OTEP
0
1
Description
Forced termination of TO8P by down-counter terminate trigger is disabled
(Initial value)
Forced termination of TO8P by down-counter terminate trigger is enabled
Rev.2.0, 07/03, page 320 of 960