SH7055S Datasheet, PDF (251/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Block Diagram of Channel 1: Figure 11.3 shows a block diagram of ATU-II channel 1.
STR1A/1B, 2B
Prescaler 1
TCLKA
TCLKB
TI10 (AGCK)
TI10 multiplication
(AGCKM)
TIO1A
TIO1B
TIO1C
TIO1D
TIO1E
TIO1F
TIO1G
TIO1H
Clock selection
logic
(2 systems: A, B)
GR1A
GR1B
GR1C
GR1D
GR1E
GR1F
GR1G
GR1H
OSBR1
TCNT1A
OCR1
TCNT1B
TIOR1A
TIOR1B
TIOR1C
TIOR1D
TCR1A
TCR1B
TSR1A
TSR1B
TIER1A
TIER1B
TRGMDR
Control
logic
I/O control
Internal data bus and address bus
Compa-
rator
TI0A(capture signal from CH0)
TRG1A
(counter clear trigger
from CH10)
TRG1B
(counter clear trigger
from CH10)
One-shot start
trigger (CH8)
One-shot terminate
trigger (CH8)
Overflow interrupt × 1
Input capture/output
compare interrupts × 8
Figure 11.3 Block Diagram of Channel 1
Rev.2.0, 07/03, page 213 of 960