SH7055S Datasheet, PDF (430/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Start
Select counter clock 1
Set port-ATU-II connection 2
Set input waveform edge
detection
3
Start counter
4
Input capture operation
Figure 11.53 Sample Setup Procedure for Input Capture
Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of
the setup procedure for waveform output by output compare-match is shown in figure 11.54.
1. Select the first-stage counter clock ø' in prescaler register (PSCR), and the second-stage
counter clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, also select the external clock edge type with the CKEG bit in TCR.
2. Set the port control register corresponding to the waveform output port to ATU output
compare-match output. Also set the corresponding bit to 1 in the port IO register to specify the
output attribute for the port.
3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control
register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on output
compare-match by making the appropriate setting in the interrupt enable register (TIER).
4. Set the timing for compare-match generation in the ATU general register (GR) corresponding
to the port set in 2.
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT). Waveform output is performed from the relevant port when the TCNT value
and GR value match.
Rev.2.0, 07/03, page 392 of 960