SH7055S Datasheet, PDF (316/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 0—Input Capture/Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A
input capture or compare-match.
Bit 0: IMF11A
0
1
Description
[Clearing condition]
(Initial value)
When IMF11A is read while set to 1, then 0 is written to IMF11A
[Setting conditions]
• When the TCNT11 value is transferred to GR11A by an input capture
signal while GR11A is functioning as an input capture register
• When TCNT11 = GR11A while GR11A is functioning as an output
compare register
11.2.6 Timer Interrupt Enable Registers (TIER)
The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers:
one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5.
For details of channel 10, see section 11.2.26, Channel 10 Registers.
Channel
0
1
2
3
4
5
6
7
8
9
11
Abbreviation
TIER0
TIER1A, TIER1B
TIER2A, TIER2B
TIER3
Function
Controls input capture, and overflow interrupt request
enabling/disabling.
Control input capture, compare-match, and overflow interrupt
request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
TIER6
TIER7
TIER8
TIER9
TIER11
Control cycle register compare-match interrupt request
enabling/disabling.
Controls down-counter output end (low) interrupt request
enabling/disabling.
Controls event counter compare-match interrupt request
enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
The TIER registers are 16-bit readable/writable registers that control enabling/disabling of free-
running counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests,
channel 1 to 5 and 11 general register input capture/compare-match interrupt requests, channel 6
and 7 compare-match interrupt requests, channel 8 down-counter output end interrupt requests,
and channel 9 event counter compare-match interrupt requests.
Rev.2.0, 07/03, page 278 of 960