SH7055S Datasheet, PDF (554/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16 clocks
8 clocks
0
78
15 0
78
Base clock
–7.5 clocks +7.5 clocks
Receive
data (RxD)
Start bit
D0
15 0
5
D1
Synchronization
sampling timing
Data
sampling timing
Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as:
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0–1.0)
L : Frame length (L = 9–12)
F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
15.5.7 Constraints on DMAC Use
• When using an external clock source for the serial clock, update TDR with the DMAC, and
then after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If a transmit
clock is input in the first four Pφ clocks after TDR is written, an error may occur (figure
15.26).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
(RXI) interrupt of the SCI as a start-up source.
Rev.2.0, 07/03, page 516 of 960