SH7055S Datasheet, PDF (322/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B)
TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and
overflow interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVE2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit:
Initial value:
R/W:
7
IME2H
0
R/W
6
IME2G
0
R/W
5
IME2F
0
R/W
4
IME2E
0
R/W
3
IME2D
0
R/W
2
IME2C
0
R/W
1
IME2B
0
R/W
0
IME2A
0
R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by
OVF2A in TSR2A when OVF2A is set to 1.
Bit 8: OVE2A
0
1
Description
OVI2A interrupt requested by OVF2A is disabled
OVI2A interrupt requested by OVF2A is enabled
(Initial value)
• Bit 7—Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables
interrupt requests by IMF2H in TSR2A when IMF2H is set to 1.
Bit 7: IME2H
0
1
Description
IMI2H interrupt requested by IMF2H is disabled
IMI2H interrupt requested by IMF2H is enabled
(Initial value)
• Bit 6—Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables
interrupt requests by IMF2G in TSR2A when IMF2G is set to 1.
Bit 6: IME2G
0
1
Description
IMI2G interrupt requested by IMF2G is disabled
IMI2G interrupt requested by IMF2G is enabled
(Initial value)
Rev.2.0, 07/03, page 284 of 960