SH7055S Datasheet, PDF (27/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.1.2 Block Diagram ..................................................................................................... 158
10.1.3 Register Configuration......................................................................................... 159
10.2 Register Descriptions ........................................................................................................ 160
10.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 160
10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 161
10.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 161
10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 162
10.2.5 DMAC Operation Register (DMAOR) ................................................................ 167
10.3 Operation .......................................................................................................................... 169
10.3.1 DMA Transfer Flow ............................................................................................ 169
10.3.2 DMA Transfer Requests ...................................................................................... 171
10.3.3 Channel Priority ................................................................................................... 174
10.3.4 DMA Transfer Types........................................................................................... 174
10.3.5 Dual Address Mode ............................................................................................. 174
10.3.6 Bus Modes ........................................................................................................... 180
10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer
Category............................................................................................................... 181
10.3.8 Bus Mode and Channel Priorities ........................................................................ 182
10.3.9 Source Address Reload Function......................................................................... 182
10.3.10 DMA Transfer Ending Conditions....................................................................... 183
10.3.11 DMAC Access from CPU.................................................................................... 184
10.4 Examples of Use ............................................................................................................... 185
10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory.......... 185
10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory
(Address Reload On)............................................................................................ 185
10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting
Side (Indirect Address on) ................................................................................... 187
10.5 Usage Notes ...................................................................................................................... 189
Section 11 Advanced Timer Unit-II (ATU-II)...................................................191
11.1 Overview........................................................................................................................... 191
11.1.1 Features................................................................................................................ 191
11.1.2 Pin Configuration................................................................................................. 197
11.1.3 Register Configuration......................................................................................... 201
11.1.4 Block Diagrams ................................................................................................... 211
11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram...................... 221
11.1.6 Prescaler Diagram................................................................................................ 222
11.2 Register Descriptions ........................................................................................................ 223
11.2.1 Timer Start Registers (TSTR) .............................................................................. 223
11.2.2 Prescaler Registers (PSCR).................................................................................. 227
11.2.3 Timer Control Registers (TCR) ........................................................................... 228
11.2.4 Timer I/O Control Registers (TIOR).................................................................... 238
11.2.5 Timer Status Registers (TSR) .............................................................................. 249
Rev.2.0, 07/03, page xxvii of xxxviii