SH7055S Datasheet, PDF (339/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 6—A/D2 Converter Interval Activation Bit 8 (ITVA8): A/D2 converter activation setting
bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVA8, and
the result is output to the A/D2 converter as an activation signal.
Bit 6: ITVA8
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 8 is disabled
A/D2 converter activation by rise of TCNT0 bit 8 is enabled
(Initial value)
• Bit 5—A/D2 Converter Interval Activation Bit 7 (ITVA7): A/D2 converter activation setting
bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVA7, and
the result is output to the A/D2 converter as an activation signal.
Bit 5: ITVA7
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 7 is disabled
A/D2 converter activation by rise of TCNT0 bit 7 is enabled
(Initial value)
• Bit 4—A/D2 Converter Interval Activation Bit 6 (ITVA6): A/D2 converter activation setting
bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVA6, and
the result is output to the A/D2 converter as an activation signal.
Bit 4: ITVA6
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 6 is disabled
A/D2 converter activation by rise of TCNT0 bit 6 is enabled
(Initial value)
• Bit 3—Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit
9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in
TSR0, and an interrupt request is sent to the CPU.
Bit 3: ITVE9
0
1
Description
Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled
Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled
(Initial value)
• Bit 2—Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit
8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in
TSR0, and an interrupt request is sent to the CPU.
Bit 2: ITVE8
0
1
Description
Interrupt request (ITV1) by rise of TCNT0 bit 8 is disabled
Interrupt request (ITV1) by rise of TCNT0 bit 8 is enabled
(Initial value)
Rev.2.0, 07/03, page 301 of 960