SH7055S Datasheet, PDF (25/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

6.5.4 General Illegal Instructions.................................................................................. 90
6.5.5 Floating-Point Instructions................................................................................... 90
6.6 When Exception Sources Are Not Accepted .................................................................... 91
6.7 Stack Status after Exception Processing Ends .................................................................. 92
6.8 Usage Notes ...................................................................................................................... 93
6.8.1 Value of Stack Pointer (SP) ................................................................................. 93
6.8.2 Value of Vector Base Register (VBR) ................................................................. 93
6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 93
6.8.4 Interrupt Processing Timing Gap Caused in SCO Processing ............................. 93
Section 7 Interrupt Controller (INTC) ...............................................................95
7.1 Overview........................................................................................................................... 95
7.1.1 Features................................................................................................................ 95
7.1.2 Block Diagram ..................................................................................................... 96
7.1.3 Pin Configuration................................................................................................. 97
7.1.4 Register Configuration......................................................................................... 97
7.2 Interrupt Sources............................................................................................................... 98
7.2.1 NMI Interrupts ..................................................................................................... 98
7.2.2 User Break Interrupt ............................................................................................ 98
7.2.3 H-UDI Interrupt ................................................................................................... 98
7.2.4 IRQ Interrupts ...................................................................................................... 98
7.2.5 On-Chip Peripheral Module Interrupts ................................................................ 99
7.2.6 Interrupt Exception Vectors and Priority Rankings ............................................. 100
7.3 Description of Registers.................................................................................................... 109
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL) ................................................... 109
7.3.2 Interrupt Control Register (ICR).......................................................................... 110
7.3.3 IRQ Status Register (ISR).................................................................................... 111
7.4 Interrupt Operation............................................................................................................ 113
7.4.1 Interrupt Sequence ............................................................................................... 113
7.4.2 Stack after Interrupt Exception Processing .......................................................... 115
7.5 Interrupt Response Time................................................................................................... 116
7.6 Data Transfer with Interrupt Request Signals ................................................................... 118
7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 118
7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 118
Section 8 User Break Controller (UBC) ............................................................119
8.1 Overview........................................................................................................................... 119
8.1.1 Features................................................................................................................ 119
8.1.2 Block Diagram ..................................................................................................... 120
8.1.3 Register Configuration......................................................................................... 121
8.2 Register Descriptions ........................................................................................................ 121
8.2.1 User Break Address Register (UBAR)................................................................. 121
8.2.2 User Break Address Mask Register (UBAMR) ................................................... 122
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