SH7055S Datasheet, PDF (200/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

The value after a power-on reset and in standby mode is undefined.
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
designate the operation and transmission of each channel. CHCR register bits are initialized to
H'00000000 by a power-on reset and in standby mode.
Bit: 31
30
29
28
27
26
25
24
—
—
—
DI
—
—
—
RO
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W*²
R
R
R
R/W*²
Bit: 23
22
21
20
19
18
17
16
—
—
—
RS4 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W R/W*¹ R/W
Rev.2.0, 07/03, page 162 of 960