SH7055S Datasheet, PDF (327/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 13—Input Capture/Compare-Match Interrupt Enable 5D (IME5D): Enables or disables
interrupt requests by IMF5D in TSR3 when IMF5D is set to 1.
Bit 13: IME5D
0
1
Description
IMI5D interrupt requested by IMF5D is disabled
IMI5D interrupt requested by IMF5D is enabled
(Initial value)
• Bit 12—Input Capture/Compare-Match Interrupt Enable 5C (IME5C): Enables or disables
interrupt requests by IMF5C in TSR3 when IMF5C is set to 1.
Bit 12: IME5C
0
1
Description
IMI5C interrupt requested by IMF5C is disabled
IMI5C interrupt requested by IMF5C is enabled
(Initial value)
• Bit 11—Input Capture/Compare-Match Interrupt Enable 5B (IME5B): Enables or disables
interrupt requests by IMF5B in TSR3 when IMF5B is set to 1.
Bit 11: IME5B
0
1
Description
IMI5B interrupt requested by IMF5B is disabled
IMI5B interrupt requested by IMF5B is enabled
(Initial value)
• Bit 10—Input Capture/Compare-Match Interrupt Enable 5A (IME5A): Enables or disables
interrupt requests by IMF5A in TSR3 when IMF5A is set to 1.
Bit 10: IME5A
0
1
Description
IMI5A interrupt requested by IMF5A is disabled
IMI5A interrupt requested by IMF5A is enabled
(Initial value)
• Bit 9—Overflow Interrupt Enable 4 (OVE4): Enables or disables interrupt requests by OVF4
in TSR3 when OVF4 is set to 1.
Bit 9: OVE4
0
1
Description
OVI4 interrupt requested by OVF4 is disabled
OVI4 interrupt requested by OVF4 is enabled
(Initial value)
Rev.2.0, 07/03, page 289 of 960