SH7055S Datasheet, PDF (555/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less.
Figure 15.26 Example of Synchronous Transmission with DMAC
15.5.8 Cautions on Synchronous External Clock Mode
• Set TE = RE = 1 only when external clock SCK is 1.
• Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is cleared to zero 2.5–3.5 Pφ clocks after the rising edge
of the RxD D7 bit SCK input, but copying to RDR is not possible.
15.5.9 Caution on Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is cleared to zero 1.5 Pφ clocks after the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
Rev.2.0, 07/03, page 517 of 960