SH7055S Datasheet, PDF (664/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Serial data
Instruc-
Input/
tion SDTRF Input
output
1
0
1
H-UDI interrupt
request
SDTRF _Shift
(in SDSR)^*1 enabled
SDSR and SDDR
MUX^*2
SDDR access
state
Shift
disabled _Shift
enabled
SDSR SDDR
SDSR
SDDR
Shift
CPU
Shift
CPU
SDSR serial transfer
(monitoring)
Notes: *1 SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer
data input/output to SDDR is possible.
1 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0.
0 SDDR is shift-disabled. SDDR access by the CPU is enabled.
Conditions:
•o SDTRF = 1
— When
=0
— When the CPU writes 1
— In bypass mode
• SDTRF = 0
— End of SDDR shift access in serial transfer
*2 SDSR/SDDR (Update-DR state) internal MUX switchover timing
• Switchover from SDSR to SDDR: On completion of serial transfer in which
SDTRF = 1 is output from TDO
• Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
Figure 18.2 Data Input/Output Timing Chart (1)
Rev.2.0, 07/03, page 626 of 960