SH7055S Datasheet, PDF (81/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.10 Classification of Instructions
Operation
Classification Types Code
Function
No. of
Instructions
Data transfer 5
MOV
Data transfer, immediate data transfer,
39
peripheral module data transfer, structure data
transfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Arithmetic 21 ADD
Binary addition
33
operations
ADDC Binary addition with carry
ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1
Division
DIV0S Initialization of signed division
DIV0U Initialization of unsigned division
DMULS Signed double-length multiplication
DMULU Unsigned double-length multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, double-length
multiply-and-accumulate operation
MUL
Double-length multiply operation
MULS Signed multiplication
MULU Unsigned multiplication
NEG
Negation
NEGC Negation with borrow
SUB
Binary subtraction
SUBC Binary subtraction with borrow
SUBV
Binary subtraction with underflow
Rev.2.0, 07/03, page 43 of 960