SH7055S Datasheet, PDF (428/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.5.4 8-Bit or 16-Bit Accessible Registers
The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A,
TCR7B), timer I/O control registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A,
TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the timer start register (TSTR1, TSTR2,
TSTR3) are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the
internal 16-bit data bus, and can be read or written a byte at a time.
In addition, a pair of 8-bit registers for which only the least significant bit of the address is
different, such as timer I/O control register 1A (TIOR1A) and timer I/O control register 1B
(TIOR1B), can be read or written in combination a word at a time.
Figures 11.49 and 11.50 show the operation when performing individual byte read or write
accesses to TIOR1A and TIOR1B. Figure 11.51 shows the operation when performing a word
read or write access to TIOR1A and TIOR1B simultaneously.
CPU
Internal data bus
Only upper 8 bits used
Bus
interface
Module data bus
Only upper 8 bits used
Figure 11.49 Byte Read/Write Access to TIOR1B
TIOR1B
TIOR1A
CPU
Internal data bus
Only lower 8 bits used
Bus
interface
Module data bus
Only lower 8 bits used
Figure 11.50 Byte Read/Write Access to TIOR1A
TIOR1B
TIOR1A
CPU
Internal data bus
Bus
interface
Module data bus
TIOR1B
TIOR1A
Figure 11.51 Word Read/Write Access to TIOR1A and TIOR1B
Rev.2.0, 07/03, page 390 of 960