SH7055S Datasheet, PDF (605/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.3.4 Receive Mode
Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is
described below, and a reception flowchart is shown in figure 16.11.
1. Initialization (after hardware reset only)
a. Clearing of IRR0 bit in interrupt register (IRR)
b. HCAN pin port settings
c. Bit rate settings
d. Mailbox transmit/receive settings
e. Mailbox initialization
2. Interrupt and receive message settings
a. Interrupt setting
b. Arbitration field setting
c. Local acceptance filter mask (LAFM) settings
3. Message reception and interrupts
a. Message reception CRC check
b. Data frame reception
c. Remote frame reception
d. Unread message reception
Initialization (after Hardware Reset Only): These settings should be made while the HCAN is
in bit configuration mode.
1. IRR0 clearing
The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software
standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled,
IRR0 should be cleared.
2. HCAN pin port settings
To prevent erroneous identification of CAN bus data, HCAN pin port settings should be made
first. See HCAN Pin Port Settings in section 16.3.2, Initialization after a Hardware Reset, and
section 20, Pin Function Controller (PFC), for details.
3. Bit rate settings
Set values relating to the CAN bus communication speed and re-synchronization. See Bit Rate
Settings in section 16.3.2, Initialization after a Hardware Reset, for details.
4. Mailbox transmit/receive settings
Each channel has one receive-only mailbox (mailbox 0) and 15 mailboxes that can be set for
reception. Thus a total of 32 mailboxes can be used for reception. To set a mailbox for
reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The
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