SH7055S Datasheet, PDF (745/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 21.2 Port A Data Register (PADR) Read/Write Operations
Bits 15 to 0:
PAIOR
Pin Function
0
General input
Other than
general input
1
General output
Other than
general output
Read
Pin state
Pin state
PADR value
PADR value
Write
Value is written to PADR, but does not affect pin
state
Value is written to PADR, but does not affect pin
state
Write value is output from pin
Value is written to PADR, but does not affect pin
state
21.2.3 Port A Port Register (PAPR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR
Initial value: * * * * * * * * * * * * * * * *
R/W: R R R R R R R R R R R R R R R R
Note: * The initial value is 1 when the PA15 to PA0 pins are high, and it is 0 when the pins are low.
The port A port register (PAPR) is a 16-bit read-only register that always stores the value of the
port A pins. The CPU cannot write data to this register. Bits PA15PR to PA0PR correspond to
pins PA15/RxD0 to PA0/TI0A. If PAPR is read, the corresponding pin values are returned.
• Bits 15 to 0: Port A15 to A0 Port Register (PA15PR to PA0PR)
PA15PR to PA0PR
0
1
Description
Low-level signals are output from or input to the PA15 to PA0 pins.
High-level signals are output from or input to the PA15 to PA0 pins.
Rev.2.0, 07/03, page 707 of 960