SH7055S Datasheet, PDF (315/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Status Register 11 (TSR11)
TSR11 indicates the status of channel 11 input capture, compare-match, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVF11
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
— IMF11B IMF11A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow.
Bit 8: OVF11
0
1
Description
[Clearing condition]
(Initial value)
When OVF11 is read while set to 1, then 0 is written to OVF11
[Setting condition]
When the TCNT11 value overflows (from H'FFFF to H'0000)
• Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 1—Input Capture/Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B
input capture or compare-match.
Bit 1: IMF11B
0
1
Description
[Clearing condition]
(Initial value)
When IMF11B is read while set to 1, then 0 is written to IMF11B
[Setting conditions]
• When the TCNT11 value is transferred to GR11B by an input capture
signal while GR11B is functioning as an input capture register
• When TCNT11 = GR11B while GR11B is functioning as an output
compare register
Rev.2.0, 07/03, page 277 of 960